Computer memory

Results: 7013



#Item
61Soundness of Data Flow Analyses for Weak Memory Models⋆ Jade Alglave, Daniel Kroening, John Lugton, Vincent Nimal, and Michael Tautschnig Department of Computer Science, University of Oxford, UK

Soundness of Data Flow Analyses for Weak Memory Models⋆ Jade Alglave, Daniel Kroening, John Lugton, Vincent Nimal, and Michael Tautschnig Department of Computer Science, University of Oxford, UK

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Source URL: www0.cs.ucl.ac.uk

Language: English - Date: 2012-09-10 07:41:01
62Attested Append-Only Memory: Making Adversaries Stick to their Word Byung-Gon Chun† Petros Maniatis⋆ Scott Shenker†‡ †

Attested Append-Only Memory: Making Adversaries Stick to their Word Byung-Gon Chun† Petros Maniatis⋆ Scott Shenker†‡ †

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Source URL: www.sosp2007.org

Language: English - Date: 2016-06-15 13:09:51
63Lecture 23: More on Pointto-Point Communication William Gropp www.cs.illinois.edu/~wgropp Cooperative Operations for Communication

Lecture 23: More on Pointto-Point Communication William Gropp www.cs.illinois.edu/~wgropp Cooperative Operations for Communication

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Source URL: wgropp.cs.illinois.edu

Language: English - Date: 2015-03-05 17:42:20
64Composable Architecture for Rack Scale Big Data Computing  Chung-Sheng Li1, Hubertus Franke1, Colin Parris2, Bulent Abali1, Mukil Kesavan3, Victor Chang4 1. IBM Thomas J. Watson Research Center, Yorktown Heights, NY 1059

Composable Architecture for Rack Scale Big Data Computing Chung-Sheng Li1, Hubertus Franke1, Colin Parris2, Bulent Abali1, Mukil Kesavan3, Victor Chang4 1. IBM Thomas J. Watson Research Center, Yorktown Heights, NY 1059

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Source URL: eprints.soton.ac.uk

Language: English - Date: 2016-07-21 12:31:14
65cs281: Introduction to Computer Systems  Prelab for Lab06 – Introduction to Sequential Circuits Overview In this lab, we will learn about designing circuits that utilize memory (and a clock) in order to achieve some

cs281: Introduction to Computer Systems Prelab for Lab06 – Introduction to Sequential Circuits Overview In this lab, we will learn about designing circuits that utilize memory (and a clock) in order to achieve some

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Source URL: personal.denison.edu

Language: English - Date: 2015-11-10 08:26:32
66Precise Automatable Analytical Modeling of the Cache Behavior of Codes with Indirections ´ DOALLO DIEGO ANDRADE, BASILIO B. FRAGUELA, and RAMON Universidade da Coruna

Precise Automatable Analytical Modeling of the Cache Behavior of Codes with Indirections ´ DOALLO DIEGO ANDRADE, BASILIO B. FRAGUELA, and RAMON Universidade da Coruna

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Source URL: www.des.udc.es

Language: English - Date: 2008-02-19 05:12:01
67Software Verification for Weak Memory via Program Transformation⋆ Jade Alglave1,2 , Daniel Kroening2, Vincent Nimal2 , and Michael Tautschnig2,3 1  3

Software Verification for Weak Memory via Program Transformation⋆ Jade Alglave1,2 , Daniel Kroening2, Vincent Nimal2 , and Michael Tautschnig2,3 1 3

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Source URL: www0.cs.ucl.ac.uk

Language: English - Date: 2013-01-23 08:25:46
68Lecture 8: The Cache Oblivious Approach www.cs.illinois.edu/~wgropp Designing for Memory Hierarchy

Lecture 8: The Cache Oblivious Approach www.cs.illinois.edu/~wgropp Designing for Memory Hierarchy

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Source URL: wgropp.cs.illinois.edu

Language: English - Date: 2015-01-15 10:21:32
69Understanding POWER Multiprocessors Susmit Sarkar1 1 Peter Sewell1

Understanding POWER Multiprocessors Susmit Sarkar1 1 Peter Sewell1

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Source URL: www0.cs.ucl.ac.uk

Language: English
70Windows Server 2012 R2 SMB Performance RDMA vs. NIC Throughput, IOPS and CPB Executive Summary A most notable feature of Windows Server 2012 R2 is the release of SMB 3.0, which seamlessly leverages RDMA-enabled adapters

Windows Server 2012 R2 SMB Performance RDMA vs. NIC Throughput, IOPS and CPB Executive Summary A most notable feature of Windows Server 2012 R2 is the release of SMB 3.0, which seamlessly leverages RDMA-enabled adapters

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Source URL: www.chelsio.com

Language: English - Date: 2014-03-18 09:17:18